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| CXD2586R/-1 CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD2586R/-1 is a digital signal processor LSI for CD players. This LSI incorporates the digital servo, digital filter and 1-bit DAC. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a builtin RAM Digital Signal Processor Block * Playback mode which supports CAV (Constant Angular Velocity) * Frame jitter free * Half-speed to octuple-speed continuous playback possible with a low external clock (only CXD2586R-1 supports up to octuple speed) * Allows relative rotational velocity readout * Wide capture range playback mode * Spindle rotational velocity following method * Supports normal-speed, double-speed, quadruplespeed, sextuple-speed and octuple-speed playback (only CXD2586R-1) * Wide frame jitter margin (28 frames) due to a built-in 32K RAM * The bit clock, which strobes the EFM signal, is generated by the digital PLL * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction * Octuple-speed (only CXD2586R-1), sextuple-speed, quadruple-speed and double-speed playback (digital signal processor and digital servo blocks) * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and Sub Q data error detection * Digital spindle servo (with oversampling filter) * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high accuracy * Digital audio interface outputs * Digital level meter, peak meter * Bilingual compatible Digital Servo Block * Microcomputer software-based flexible servo control * Servo error signal, offset cancel function * Servo loop, auto gain control function * E:F balance, focus bias adjustment function Digital Filters (DAC and LPF blocks) * Low-pass filter for DAC * Digital de-emphasis * Digital attenuation * 4fs oversampling filter * Adopts secondary noise shaper * LPF for DAC analog output 144 pin LQFP (Plastic) Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD -0.3 to +7.0 V * Input voltage VI -0.3 to +7.0 V (VSS - 0.3V to VDD +0.3V) * Output voltage VO -0.3 to +7.0 V * Storage temperature Tstg -40 to +125 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V Recommended Operating Conditions * Supply voltage * Operating temperature The VDD (min.) for the CXD2586R/-1 varies according to the playback speed and built-in VCO selection. The VDD (min.) is 4.5V when high-speed VCO and quadruple-speed playback are selected (variable pitch off). The VDD (min.) for the CXD2586R/-1 under various conditions are as shown in the following table. Playback speed x8 (only CXD2586R-1) x6 x4 x 21 x2 x 12 x1 VDD (min.) [V] VCO1 high VCO1 normal speed speed 4.75 4.50 4.50 4.00 3.40 3.40 3.40 -- -- -- -- 4.00 3.40 3.40 DAC block -- -- -- -- -- -- 4.50 --: Dashes indicate that there is no assurance of the processor operating. All values are for variable pitch off. 1 When the internal operation of the LSI is set to normalspeed playback and the operating clock of the signal processor is doubled, double-speed playback results. 2 When the internal operation of the LSI is set to doublespeed mode and the crystal oscillating frequency is halved in low power consumption mode, normal-speed playback results. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95Y01A65-ST CXD2586R/-1 Block Diagram VPCO1 VPCO2 PCMDI ACDT DTS1 BCKI LRCKI XTLO DTS3 DTS2 DTS4 DTS5 DTS6 XTLI DTS7 XTSL 52 53 4 5 105 72 62 63 64 65 66 67 68 25 27 23 DAC block 58 AOUT1 MCKO 73 MCLK 74 VPCO1, 2 4, 5 VCKI 135 FSTO 76 C4M 77 C16M 78 PDO 134 VCOI 128 VCOO 127 PCO 9 FILI 8 FILO 7 CLTV 10 RFAC 12 ASYI 14 ASYO 15 ASYE 19 WFCK 83 SCOR 84 EXCK 86 SBSO 85 SQCK 88 SQSO 87 MON 108 FSW 107 MDP 110 MDS 111 CLV processor Timing Generator1 Subcode P to W processor Digital out Subcode Q processor Error corrector Peak detector MUX Sync protector D/A data processor Digital PLL Vari-Pitch double speed EFM Demodulator Clock Generator 32K RAM 4fs Digital Filter + 1 bit DAC LPF 57 AIN1 56 LOUT1 47 AOUT2 LPF 48 AIN2 49 LOUT2 Register Address generator 8 Priority encoder Serial/parallel processor 20 PSSL 42 to 31, 29, 28, DA01 to DA16 26, 24 82 MUTE 80 DOUT 79 MD2 96 DATA CPU interface 98 CLOK 97 XLAT Timing Generator2 Servo auto sequencer Noise Shaper PWMI 106 VCTL 6 V16M 136 OSC 18-times oversampling filter 89 SENS Servo Interface MIRR DFCT FOK Servo block 2 PWM GENERATOR SERVO DSP OpAmp AnaSw A/D CONVERTER FOCUS SERVO TRACKING SERVO SLED SERVO FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR 2 2 2 2 2 99 COUT 102 MIRR 103 DFCT 104 FOK 114, 117 SFDR, SFON 116, 115 SRDR, SRON 118, 121 TFDR, TFON 120, 119 TRDR, TRON 122, 125 FFDR, FFON 124, 123 FRDR, FRON Signal processor block RFDC 142 CE 143 TE 144 SE 1 FE 2 VC 3 141 140 129 131 132 18 101 126 16 137 59 46 51 43 81 130 11 139 55 60 45 50 54 91 AVDD1 DVSS3 AVSS32 AVDD3 DVDD3 AVDD5 DVSS2 AVSS41 AVDD4 -2- AVSS31 AVSS42 DVDD2 DVSS1 DVDD0 AVDD2 AVSS1 AVSS2 AVSS5 XRST TEST TES2 TES3 ADIO RFC CXD2586R/-1 Pin Configuration TESTA DVDD2 WFCK DFSW DVSS2 SQSO SCOR COUT SQCK MUTE DOUT SBSO PWMI SENS EXCK DFCT SCLK FSTO MIRR FSW MD2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC. 109 MDP 110 MDS 111 LOCK 112 SSTP 113 SFDR 114 SRON 115 SRDR 116 SFON 117 TFDR 118 TRON 119 TRDR 120 TFON 121 FFDR 122 FRON 123 FRDR 124 FFON 125 DVDD3 126 VCOO 127 VCOI 128 TEST 129 DVSS3 130 TES2 131 TES3 132 NC. 133 PDO 134 VCKI 135 V16M 136 AVDD2 137 IGEN 138 AVSS2 139 ADIO 140 RFC 141 RFDC 142 CE 143 TE 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 XTSL 71 DAS1 70 DAS0 69 XWO 68 DTS7 67 DTS6 66 DTS5 65 DTS4 64 DTS3 63 DTS2 62 DTS1 61 NC. 60 AVSS32 59 AVDD3 58 AOUT1 57 AIN1 56 LOUT1 55 AVSS31 54 AVSS5 53 XTLI 52 XTLO 51 AVDD5 50 AVSS42 49 LOUT2 48 AIN2 47 AOUT2 46 AVDD4 45 AVSS41 44 NC. 43 DVSS1 42 DA01 41 DA02 40 DA03 39 DA04 38 DA05 37 DA06 FILI LRCKI C4M FOK NC. DA14 DVDD1 LRCK VPCO2 WDCK DA13 CLTV AVSS1 PSSL DA15 DA11 DA10 BCKI PCO NC. VC FSTI DA08 MCLK CLOK ATSK DIRC VPCO1 PCMDI AVDD1 VCTL RFAC ASYO -3- ASYE DA16 DA12 DA09 DA07 FE BIAS SE FILO ASYI NC. MCKO XRST MON DATA XLAT C16M NC. CXD2586R/-1 Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 Symbol SE FE VC VPCO1 VPCO2 VCTL FILO FILI PCO CLTV AVSS1 RFAC BIAS ASYI ASYO AVDD1 DVDD1 ASYE PSSL WDCK LRCK LRCKI DA16 PCMDI DA15 BCKI DA14 DA13 DA12 DA11 DA10 DA09 DA08 DA07 I I O O I O I O I O O O O O O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 I I I O 1, 0 I I I O O I O I O I 1, Z, 0 Analog 1, Z, 0 1, Z, 0 I/O Sled error signal input. Focus error signal input. Center voltage input. Wide-band EFM PLL VCO2 charge pump output. Wide-band EFM PLL VCO2 charge pump output. Wide-band EFM PLL VCO2 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Master VCO control voltage input. Analog GND. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). Analog power supply. Digital power supply. Asymmetry circuit on/off (low = off, high = on). Audio data output mode switching input (low = serial, high = parallel). D/A interface for 48-bit slot. Word clock f = 2Fs. D/A interface for 48-bit slot. LR clock f = Fs. LR clock input to DAC (48-bit slot). DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's complement, MSB first) when PSSL = 0. Audio data input to DAC (48-bit slot). DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0. Bit clock input to DAC (48-bit slot). DA14 output when PSSL = 1, 64-bit slot serial data output (two's complement, LSB first) when PSSL = 0. DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0. DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0. DA11 output when PSSL = 1, GTOP output when PSSL = 0. DA10 output when PSSL = 1, XUGF output when PSSL = 0. DA09 output when PSSL = 1, XPLCK output when PSSL = 0. DA08 output when PSSL = 1, GFS output when PSSL = 0. DA07 output when PSSL = 1, RFCK output when PSSL = 0. Description -4- CXD2586R/-1 Pin No. 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol DA06 DA05 DA04 DA03 DA02 DA01 DVSS1 AVSS41 AVDD4 AOUT2 AIN2 LOUT2 AVSS42 AVDD5 XTLO XTLI AVSS5 AVSS31 LOUT1 AIN1 AOUT1 AVDD3 AVSS32 DTS1 DTS2 DTS3 DTS4 DTS5 DTS6 DTS7 XWO DAS0 DAS1 XTSL MCKO MCLK FSTI I I I I I O I I I I O I O O I O I O O O O O O O I/O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Description DA06 output when PSSL = 1, C2PO output when PSSL = 0. DA05 output when PSSL = 1, XRAOF output when PSSL = 0. DA04 output when PSSL = 1, MNT3 output when PSSL = 0. DA03 output when PSSL = 1, MNT2 output when PSSL = 0. DA02 output when PSSL = 1, MNT1 output when PSSL = 0. DA01 output when PSSL = 1, MNT0 output when PSSL = 0. Digital GND. Analog GND. Analog power supply. Analog Channel 2 analog output. Channel 2 analog input. Analog Channel 2 LINE output. Analog GND. Master clock power supply. 1, 0 Master clock 33.8688MHz crystal oscillation circuit output. Master clock 33.8688MHz crystal oscillation circuit output. Master clock GND. Analog GND. Analog Channel 1 LINE output pin. Channel 1 analog input pin. Analog Channel 1 analog output pin. Analog power supply. Analog GND. DAC test pin. Normally fixed to high. DAC test pin. Normally fixed to high. DAC test pin. Leave this open. DAC test pin. Leave this open DAC test pin. Leave this open. DAC test pin. Leave this open. DAC test pin. Normally fixed to low. DAC sync window open input. Normally high, window open when low. DAC test pin. Normally fixed to low. DAC test pin. Normally fixed to low. Crystal selection input. 1, 0 DSP clock output. DSP clock input. 2/3 frequency division input for MCLK pin. -5- CXD2586R/-1 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 101 102 103 104 105 106 107 108 110 111 112 113 114 115 Symbol FSTO C4M C16M MD2 DOUT DVSS2 MUTE WFCK SCOR SBSO EXCK SQSO SQCK SENS XRST DIRC SCLK DFSW ATSK DATA XLAT CLOK COUT DVDD2 MIRR DFCT FOK TESTA PWMI FSW MON MDP MDS LOCK SSTP SFDR SRON I O O O O O I O O O O O I O O O I O I O I I I I I I I I O O O O I O I/O 1, 0 1, 0 1, 0 Description 2/3 frequency division output for MCLK pin. Does not change with variable pitch. 1/4 frequency division output for MCLK pin. Changes with variable pitch. 16.9344MHz output. Changes simultaneously with variable pitch. Digital Out on/off control. (low: off, high: on) 1, 0 Digital Out output pin. Digital GND. Mute (low: off, high: on) 1, 0 1, 0 1, 0 WFCK (Write Flame Clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. 1, 0 Sub Q 80-bit and PCM peak and level data 16-bit output. SQSO readout clock input. 1, 0 SENS output to CPU. System reset. Reset when low. Used during 1-track jumps. SENS serial data readout clock input. DFCT switching pin. High: DFCT countermeasure circuit off. Anti-shock pin. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. 1, 0 Track count signal output. Digital power supply. 1, 0 1, 0 1, 0 Mirror signal output. Defect signal output. Focus OK signal output. Test pin. Not connected. Spindle motor external pin input. Z, 0 1, 0 1, 0 1, 0 1, 0 Spindle motor output filter switching output. Spindle motor on/off control output. Spindle motor servo control output. Spindle motor servo control output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Disc innermost track detection signal input. 1, 0 1, 0 Sled drive output. Sled drive output. -6- CXD2586R/-1 Pin No. 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 134 135 136 137 138 139 140 141 142 143 144 Symbol SRDR SFON TFDR TRON TRDR TFON FFDR FRON FRDR FFON DVDD3 VCOO VCOI TEST DVSS3 TES2 TES3 PDO VCKI V16M AVDD2 IGEN AVSS2 ADIO RFC RFDC CE TE O I I I I I I I O I O O I I O O O O O O O O O O I/O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Focus drive output. Focus drive output. Digital power supply. 1, 0 Description Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. flock = 8.6436MHz. Test pin. Normally fixed to low. Digital GND. Test pin. Normally fixed to low. Test pin. Normally fixed to low. 1, Z, 0 Analog EFM PLL charge pump output. Variable pitch clock input from the external VCO. fcenter = 16.9344MHz. 1, 0 Wide-band EFM PLL VCO2 oscillation output. Analog power supply. Operational amplifier current source reference resistance connection. Analog GND. Operational amplifier output. RF signal LPF time constant capacitor connection. RF signal input. Center servo analog input. Tracking error signal input. In the 144-pin LQFP, the following pins are NC: Pins 17, 30, 44, 61, 90, 100, 109, and 133 Notes) * The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XRAOF is generated when the 32K RAM exceeds the 28F jitter margin. -7- CXD2586R/-1 Electrical Characteristics 1. DC Characteristics Item Input voltage (1) High level input voltage Low level input voltage High level input voltage Input voltage (2) Low level input voltage (VDD = AVDD = 5.0V 10%, Vss = AVss = 0V, Topr = -20 to +75C) Conditions VIH (1) VIL (1) VIH (2) VIL (2) Schmitt input 0.8VDD 0.2VDD Vss VDD - 0.8 0 VDD - 0.8 0 0 VDD VDD 0.4 VDD 0.4 0.4 VDD 0.4 VDD 0.4 10 20 600 5 Min. 0.7VDD 0.3VDD Typ. Max. Unit Applicable pins V V V V V V V V V V V V V V A A A A 6 7 13 1, 2, 3, 12 8 9 10 5 3, 11, 12 4 2 1 Input voltage (3) Input voltage Output voltage (1) VIN (3) Analog input High level output voltage VOH (1) IOH = -4mA Low level output voltage VOL (1) IOL = 4mA High level output voltage VOH (2) IOH = -2mA Low level output voltage VOL (2) IOL = 4mA Output voltage (2) Output voltage (1) Low level output voltage VOL (3) IOL = 4mA Output voltage (4) High level output voltage VOH (4) IOH = -0.28mA VDD - 0.5 Low level output voltage VOL (4) IOL = 0.36mA High level output voltage VOH (5) IOH = -2mA Low level output voltage VOL (5) IOL = 8mA ILI (1) ILI (2) ILI (3) ILO VI = 0 to 5.5V VI = 1.5 to 3.5V VI = 0 to 5.0V VO = 0 to 5.5V 0 VDD - 0.5 0 -10 -20 -40 -5 Output voltage (5) Input leak current (1) Input leak current (2) Input leak current (3) Tri-state pin output leak current Applicable pins 1 XTSL, DATA, XLAT, MD2, PSSL, TEST, TES2, TES3, DFSW, DIRC, SSTP, ATSK, BCKI, LRCKI, PCMDI, DTS1, DTS2, DTS7, DAS0, DAS1, XWO, PWMI 2 CLOK, XRST, EXCK, SQCK, MUTE, VCKI, ASYE, FSTI, SCLK, MCLK 3 CLTV, FILI, RFAC, ASYI, RFDC, TE, SE, FE, VC, VCTL 4 MDP, PDO, PCO, VPCO1, VPCO2 5 ASYO, DOUT, FSTO, C4M, C16M, SBSO, SQSO, SCOR, MON, LOCK, WDCK, SENS, MDS, DA01 to DA16, LRCK, WFCK, FOK, COUT, MIRR, DFCT, FFON, FRDR, FRON, FFDR, TFON, TRDR, TRON, TFDR, SFON, SRDR, SRON, SFDR, MCKO, V16M 6 FSW 7 FILO 8 TE, SE, FE, VC 9 RFDC 10 SENS, MDS, MDP, FSW, PDO, PCO, VPCO1, VPCO2 11 RFC 12 AIN1, AIN2 13 AOUT1, AOUT2, LOUT1, LOUT2 -8- CXD2586R/-1 2. AC Characteristics (1) XTLI pin, VCOI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item Symbol Min. 7 Typ. Max. 34 Unit MHz Oscillation frequency fMAX (b) When inputting pulses to XTLI and VCOI pins (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTLI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTLI and VCOI pins via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p -9- CXD2586R/-1 (2) CLOK, DATA, XLAT, SQCK, and EXCK pins (VDD = AVDD = 5.0V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750 Unit MHz ns ns ns ns ns MHz ns tWCK tSU tH tD tWL fT tWT 1/fCK tWCK tWCK CLOK DATA XLAT tSU tH tD tWL EXCK SQCK tWT 1/fT SBSO SQSO tSU tH tWT - 10 - CXD2586R/-1 (3) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 1 Unit MHz ns s tSPW tDLS 500 15 (4) COUT, MIRR and DFCT pins Operating frequency Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency (VDD = AVDD = 5.0V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Unit kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.6 to A1.3V * B = less than 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 11 - CXD2586R/-1 (5) BCKI, LRCKI and PCMDI pins Item Input BCKI frequency Input BCKI pulse width Input data setup time Input data hold time Input LRCK setup time Input LRCK hold time (VDD = 5.0V 10%, Topr = -20 to +75C) Min. Typ. Max. 4.5 100 10 15 10 15 tWIB tWIB Symbol Unit MHz tBCK tWIB tIDS tIDH tILRH tILRS ns BCKI 50% tIDS tIDH PCMDI tILRH tILRS LRCKI (6) AOUT1, AOUT2, LOUT1 and LOUT2 pins (VDD = AVDD =5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage (1) Output voltage (2) Load resistance Symbol Min. Typ. Max. 0.9VDD VDD Unit V V k Applicable pins 1 2 1, 2 VOUT (1) 0.1VDD VOUT (2) RL VSS 10 When a sine wave of 1kHz and 0dB is output. Applicable pins 1 AOUT1, AOUT2 2 LOUT1, LOUT2 - 12 - CXD2586R/-1 DAC Analog Characteristics Measurement conditions (Ta = 25C, VDD = 5.0V, FS = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768fs) Item S/N ratio THD + N Dynamic range Channel separation Output level Difference in gain between channels 1 Using "A" weighting filter 2 -60dB, 1kHz input Typ. 93 0.01 91 91 1.31 0.1 Unit dB % dB dB V (rms) dB Remarks (EIAJ) 1 (EIAJ) (EIAJ) 1, 2 (EIAJ) The analog characteristics measurement circuit is shown below. 12k AOUT1 58 12k AIN1 57 150p LOUT1 56 47 100k Audio Analyzer 12k 680p SHIBASOKU (AM51A) LPF external circuit diagram 768fs AOUT1 AIN1 TEST DISK DATA LOUT1 CXD2586 AOUT2 AIN2 LOUT2 Fs = 44.1kHz Audio Circuit 2ch Analog 1ch SHIBASOKU (AM51A) Audio Analyzer Block diagram of analog characteristics measurement - 13 - CXD2586R/-1 Contents [1] CPU Interface 1-1. CPU Interface Timing ...................................................................................................................... 15 1-2. CPU Interface Command Table ...................................................................................................... 15 1-3. CPU Command Presets .................................................................................................................. 25 1-4. Description of SENS Signals ........................................................................................................... 30 [2] Subcode Interface 2-1. P to W Subcode Readout ................................................................................................................ 57 2-2. 80-bit Sub Q Readout ...................................................................................................................... 57 [3] Description of Modes 3-1. CLV-N Mode .................................................................................................................................... 63 3-2. CLV-W Mode ................................................................................................................................... 63 3-3. CAV-W Mode ................................................................................................................................... 63 [4] Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 65 4-2. Frame Sync Protection .................................................................................................................... 67 4-3. Error Correction ............................................................................................................................... 67 4-4. DA Interface ..................................................................................................................................... 68 4-5. Digital Out ........................................................................................................................................ 71 4-6. Servo Auto Sequence ...................................................................................................................... 72 4-7. Digital CLV ....................................................................................................................................... 80 4-8. Playback Speed ............................................................................................................................... 81 4-9. DAC Block Playback Speed ............................................................................................................ 82 4-10. DAC Block Input Timing .................................................................................................................. 82 4-11. CXD2586R/-1 Clock System ........................................................................................................... 84 [5] Description of Servo Signal Processing-System Functions and Commands 5-1. General Description of the Servo Signal Processing System .......................................................... 85 5-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 86 5-3. AVRG Measurement and Compensation ........................................................................................ 86 5-4. E:F Balance Adjustment Function ................................................................................................... 88 5-5. FCS Bias Adjustment Function ........................................................................................................ 88 5-6. AGCNTL Function ........................................................................................................................... 90 5-7. FCS Servo and FCS Search ........................................................................................................... 92 5-8. TRK and SLD Servo Control ........................................................................................................... 93 5-9. MIRR and DFCT Signal Generation ................................................................................................ 94 5-10. DFCT Countermeasure Circuit ........................................................................................................ 95 5-11. Anti-Shock Circuit ............................................................................................................................ 95 5-12. Brake Circuit .................................................................................................................................... 96 5-13. COUT Signal ................................................................................................................................... 97 5-14. Serial Readout Circuit ...................................................................................................................... 97 5-15. Writing the Coefficient RAM ............................................................................................................ 98 5-16. PWM Output .................................................................................................................................... 98 5-17. DIRC Input Pin ............................................................................................................................... 100 5-18. Servo Status Changes Produced by the LOCK Signal .................................................................. 101 5-19. Description of Commands and Data Sets ..................................................................................... 101 5-20. List of Servo Filter Coefficients ...................................................................................................... 113 5-21. FILTER Composition ..................................................................................................................... 115 5-22. TRACKING and FOCUS Frequency Response ............................................................................ 122 [6] Application Circuit 6-1. Application Circuit .......................................................................................................................... 123 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: - 14 - Average Automatic gain control Focus Tracking Sled Defect CXD2586R/-1 [1] CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D18 D19 D20 D21 D22 D23 750ns or more XLAT Valid Registers * The internal registers are initialized by a reset when XRST = 0. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C to D E Total bit length 8bit 8 to 24bit 16bit 20bit 24bit 20bit 28bit 20bit 16bit 20bit - 15 - Command Table ($0X to 1X) Data 2 Data 3 Data 4 D8 D7 D4 -- -- -- -- -- FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- FOCUS SEACH VOLTAGE UP -- ANTI SHOCK ON -- ANTI SHOCK OFF -- BRAKE ON -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- -- -- TRACKING GAIN UP FILTER SELECT 2 -- CXD2586R/-1 --: Don't care D0 -- -- -- D6 D5 D3 D2 D1 -- Data 5 D12 D11 -- -- -- D10 D9 -- D16 -- -- -- -- D15 D14 D13 Address D17 -- Data 1 Register Command D23 to D20 D19 D18 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS CONTROL 0000 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- 0 1 -- -- 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 0 -- -- -- -- - 16 - 1 0 0 -- -- 1 -- 0 1 TRACKING CONTROL 0001 -- -- -- -- -- -- -- -- Command Table ($2X to 3X) Data 2 Data 3 Data 5 D4 D3 -- -- -- -- -- -- -- -- -- -- Data 5 D5 -- -- -- -- -- -- -- -- -- -- -- D4 -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- SLED KICK LEVEL (2 x basic value) -- -- SLED KICK LEVEL (3 x basic value) -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE -- D2 D1 D0 -- -- -- -- -- -- -- D12 D11 D10 -- -- -- -- -- -- -- -- -- Data 4 D8 -- D7 D6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- D9 D8 D6 D5 -- -- -- -- -- -- -- -- D7 -- -- -- -- -- -- -- -- Data 4 D16 D13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 D13 -- -- -- -- -- -- -- -- -- -- -- -- D14 -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 D15 D14 Address D17 -- -- -- -- 0 0 1 1 Data 1 D17 0 0 1 1 1 0 1 0 D16 Data 1 Register Command D23 to D20 D19 D18 0 0 0 1 1 0 1 1 2 TRACKING MODE 0010 -- -- -- -- -- -- - 17 - -- -- Address Register Command D23 to D20 D19 D18 0 0 0 0 3 SELECT 0011 0 0 0 0 CXD2586R/-1 Command Table ($340X) Address 3 D10 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN CXD2586R/-1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K00) SLED INPUT GAIN D8 D6 D5 D4 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 D3 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0000 1 1 1 1 1 1 1 1 - 18 - 3 SELECT 0011 0100 Command Table ($341X) Address 4 D10 D8 D4 D1 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L 1 1 CXD2586R/-1 D0 D3 D2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 D6 D5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0001 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 Command Table ($342X) Address 4 D10 D8 D5 D1 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K2F) NOT USED 1 1 CXD2586R/-1 D0 D4 D3 D2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0010 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 Command Table ($343X) Address 3 D10 D9 D6 D2 KRAM DATA (K30) FIX KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K3F) NOT USED 1 1 CXD2586R/-1 D1 D0 D5 D4 D3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D8 D7 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0011 1 1 1 1 1 1 1 1 - 21 - 3 SELECT 0011 0100 Command Table ($344X) Address 4 Data 2 D4 D1 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) NOT USED KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4F) NOT USED 1 1 CXD2586R/-1 D0 D3 D2 D10 D8 D5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 D6 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D9 Data 1 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0100 1 1 1 1 1 1 1 1 - 22 - 3 SELECT 0011 0100 Command Table ($34FX to 3FX) Address 2 Data 1 Data 2 D7 D4 -- FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA -- TV0 D0 D6 D5 D3 D2 D1 Data 3 D11 1 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 FB9 FB8 FB4 FB1 TV1 TV4 Data 4 D4 D3 D0 FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 0 0 0 0 SERIAL DATA READ MODE/SELECT 0 D2 D1 TV3 TV2 FB3 FB2 TV9 TV8 Data 3 D8 D7 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D6 D5 TV7 TV6 TV5 FB7 FB6 FB5 0 0 Data 2 D12 D11 FS3 TJ3 TJ2 TJ1 FS2 FS1 FS0 D10 D9 0 1 0 D10 D9 D8 D17 D14 1 1 1 1 1 1 Data 1 D17 D14 FT0 FS5 FS4 TJ4 DTZC TJ5 D13 0 1 0 1 0 1 0 1 Data 1 Data 2 D13 D11 -- -- -- -- -- -- Data 2 D12 D11 D10 D9 D8 D7 D10 -- -- -- -- D12 D9 D8 -- -- D7 -- -- D17 D14 -- -- Data 1 D17 D14 D13 1 1 1 0 0 D16 D15 0 0 1 -- 0 -- D16 D15 0 FBON FBSS FBUP FBV1 FBV0 0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 FT1 1 1 0 0 1 1 D16 D15 1 1 1 D13 D12 0 1 1 1 0 0 0 0 0 D16 D15 Address 1 Register Command D23 to D20 D19 D18 0 1 0011 0 1 0 1 Address D23 to D20 D19 D18 0 1 0 1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 - 23 - Data 3 D6 -- -- D5 -- -- Data 3 D6 D5 D4 0 0 DRR2 DRR1 DRR0 0 ASFG 0 D4 -- -- F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP AGG4 XT4D XT2D 0011 1 0 3 SELECT 1 0 1 0 TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FOCUS BIAS 0 0 Data 4 D3 -- -- D2 -- -- D1 -- -- Data 4 D3 0 D2 0 D1 D0 MIRI XT1D Filter LPAS SRO1 SRO0 AGHF COT2 Others --: Don't care D0 -- -- TZC for COUT SLCT HPTZC (Default) TZC for COUT SLCT DTZC 0 Operation for MIRR/ DFCT/FOK 1 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT Address D23 to D20 D19 D18 1 1 0011 1 1 Address D23 to D20 D19 D18 1 1 0011 CXD2586R/-1 1 1 Command Table ($4X to EX) Data 1 D0 D2 D3 D1 D2 D3 D0 -- -- -- -- D2 D1 0 0 0 D1 D0 MT1 LSSL MT0 D0 D3 MT3 MT2 D2 AS2 AS1 AS0 D1 D0 0 AS3 D3 Data 2 Data 3 Data 4 Address Register Command D3 D2 D1 4 Auto sequence 0 1 0 5 Blind (A, E), Overflow (C, G), Brake (B) 0 1 TR3 0 0 -- -- -- 0 0 TR1 0 0 0 TR0 TR2 0 1 0 -- 6 Sled KICK, KICK (F), BRAKE (D) 0 0 SD3 0 0 -- 0 0 SD1 KF2 KF1 KF0 SD0 SD2 KF3 1 1 -- -- -- 7 Auto sequence (N) track jump count setting 0 1 8192 1024 128 16 64 32 512 256 4096 32768 16384 2048 1 1 8 4 2 1 8 1 0 0 Mute 0 0 ATT DCLV DSPB ASEQ DPLL BiliGL BiliGL FLFC ON/OFF ON/OFF ON/OFF ON/OFF MAIN SUB DAC EMP DAC ATT 0 MODE setting 1 0 ASHS SOCT KSL3 KSL2 KSL1 0 0 CD- DOUT DOUT WSEL ROM Mute Mute-F VCO SEL2 VCO SEL KSL0 0 0 0 1 0 PLM3 PLM2 PLM1 PLM0 9 Function specification 1 0 0 - 24 - 1 8192 1024 512 256 32768 16384 4096 2048 128 64 0 0 VP5 1 PWM MD A Audio CTRL 1 0 1 PCT1 PCT2 DADS SOC2 AT1D7 AT1D6 AT1D5 AT1D4 AT1D3 AT1D2 AT1D1 AT1D0 B Traverse monitor counter setting 1 0 1 32 16 8 4 2 1 C DCLV TB TP VP6 CM1 VP7 CM2 CLVS Gain Spindle servo coefficient setting 1 1 0 Gain Gain Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 0 VP4 0 VP3 SFSL VC2C 0 VP2 0 VP1 0 VP0 HIFC LPWR VPON -- -- -- -- -- -- Gain Gain FCSW CAV1 CAV0 -- -- 0 --: Don't care Data 5 Data 6 D 0 CM3 CLV CTRL 1 1 0 E SPD MODE 1 1 1 CM0 EPWM SPDC ICAP Register Data 2 Command Address Data 1 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 CXD2586R/-1 AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0 A Audio CTRL 1010 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 2 D16 D13 -- -- -- -- -- -- Data 5 D4 -- -- -- D3 D2 D0 -- Data 2 D4 D3 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 + basic value) (Default) -- -- -- -- -- -- -- -- Data 4 D8 -- -- Data 1 D8 D7 D6 D5 -- -- D7 D6 D5 -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- Address 3 D12 D11 D9 D10 -- -- D11 D9 D10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D12 D9 D8 D6 D5 D4 D2 D1 D0 FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF 0 1 0 Data 2 D15 D13 -- -- -- Address 2 D17 0 0 0 D16 D15 D13 D14 D14 -- -- -- -- -- -- D15 D14 D11 D10 D7 D3 Data 3 Data 4 Data 5 Address D17 0 0 0 Data 1 D17 0 0 D16 Data 1 Register Command D23 to D20 D19 D18 0 FOCUS CONTROL 0000 0 0 1 TRACKING CONTROL 0001 0 0 2 TRACKING MODE 0010 0 0 Address Register Command D23 to D20 D19 D18 0011 0 0 Address 1 3 SELECT - 25 - See the coefficient preset values table. D23 to D20 D19 D18 0011 0 1 CXD2586R/-1 Command Preset Table ($34FX to 3FX) Address 2 Data 1 D11 D9 0 0 0 FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA 0 0 Data 4 D4 0 1 1 1 0 0 0 0 1 0 data 3 D8 -- Data 2 D12 0 0 D11 0 0 D10 0 0 0 D9 0 0 D8 0 0 D7 0 0 -- D7 D9 -- D6 -- D5 -- data 3 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D4 -- D3 -- 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Data 4 D2 -- D1 -- Data 4 D2 0 0 D1 0 0 D0 0 0 Filter Others 0 --: Don't care D0 -- TZC for COUT SLCT HPTZC (Default) -- 0 1 1 0 1 0 1 0 0 0 0 0 0 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) SERIAL DATA READ MODE/SELECT 0 FOCUS BIAS Operation for MIRR/ DFCT/FOK 0 0 0 0 0 0 0 0 0 0 0 0 Data 3 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 D6 D5 D4 D2 D1 D0 1 0 1 0 Data 2 D12 D9 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 Data 2 D13 -- -- -- D12 D11 D10 1 0 0 0 0 0 0 1 0 0 0 0 D11 D10 0 0 D10 D7 D3 Data 2 Data 3 D17 D13 1 1 1 1 1 1 D12 0 0 0 Data 1 D17 D13 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 Data 1 D17 0 -- Data 1 D17 D13 0 1 0 1 0 1 0 0 D16 D15 D14 -- 0 D16 D15 D14 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 1 D16 D15 D14 0 1 1 0 1 1 0 1 1 D16 D15 D14 Address 1 Register Command D23 to D20 D19 D18 0 1 0011 0 1 0 1 Address D23 to D20 D19 D18 0 1 0 1 0 1 - 26 - 0011 1 0 3 SELECT 1 0 1 0 1 0 Address D23 to D20 D19 D18 0011 1 1 Address D23 to D20 D19 D18 1 1 0011 CXD2586R/-1 1 1 Command Preset Table ($4X to EX) Data 1 D0 D2 D3 D0 D1 D2 -- -- -- D1 D0 0 -- 0 D0 D3 0 0 0 D3 D2 0 0 0 D2 D1 0 0 0 D1 D0 0 0 D3 Data 2 Data 3 Data 4 Address Register Command D3 D2 D1 4 Auto sequence 0 1 0 5 Blind (A, E), Brake (B), Overflow (C, G) 0 1 0 1 0 0 -- -- -- 0 0 0 0 0 0 1 0 1 0 -- 6 Sled KICK, BRAKE (D), KICK (F) 0 0 0 1 0 0 -- -- 0 0 0 0 0 0 1 1 1 1 -- -- 7 Auto sequence (N) track jump count setting 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 8 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 MODE setting 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 9 Function specification 1 0 0 - 27 - 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Data 5 Data 2 Data 3 Data 4 D3 1 D2 1 D1 1 D0 1 A Audio CTRL 1 0 1 B Traverse monitor counter setting 1 0 1 0 0 0 0 0 0 C Spindle servo coefficient setting 1 1 0 0 0 0 0 0 0 -- -- 0 -- -- 0 -- -- 0 -- -- 0 --: Don't care Data 6 D3 1 D2 1 D1 1 D0 CXD2586R/-1 1 D CLV CTRL 1 1 0 E SPD MODE 1 1 1 Register Command Address Data 1 A Audio CTRL 1010 CXD2586R/-1 - 28 - CXD2586R/-1 Fix indicates that normal preset values should be used. - 29 - CXD2586R/-1 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $38 $38 $30 to 37 $3A $3B to 3F $3904 $3908 $390C $391C $391D $391F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX ASEQ = 0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 FZC AS TZC AGOK XAVEBSY SSTP FBIAS Count STOP SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS COMP COUT OV64 0 Output data length -- -- -- -- -- -- -- -- 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit -- -- -- -- -- -- -- -- $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. - 30 - CXD2586R/-1 Description of SENS Signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg B. High when Reg B is latched, low when the initial Reg B number is input by CNIN. Counts the number of tracks set with Reg B. High when Reg B is latched, toggles each time the Reg B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. COUT OV64 - 31 - CXD2586R/-1 The meaning of the data for each address is explained below. $4X commands Register name 4 AS3 Data 1 Command AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move AS3 0 0 0 1 1 1 1 AS2 0 1 1 0 0 1 1 AS1 0 0 1 0 1 0 1 AS0 0 RXF 1 RXF RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To disable the MAX timer, set the MAX timer value to 0. $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms - 32 - CXD2586R/-1 $6X commands Register name 6 SD3 Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) Data 1 KICK (D) SD2 SD1 SD0 SD3 23.2ms 11.6ms KF3 Data 2 KICK (F) KF2 SD2 11.6ms 5.8ms KF1 KF0 SD1 5.8ms 2.9ms SD0 2.9ms 1.45ms KF3 0.72ms KF2 0.36ms KF1 0.18ms KF0 0.09ms $7X commands Auto sequence track jump count setting Command Auto sequence track jump count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 This command is to set N when a 2N track jump is executed, to set M when an M track move is executed and to set the jump count when fine search is executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal is used to count tracks for 2N-track jump/M track move; when the count is 16 or over, the MIRR signal is used. For fine search, the COUT signal is used to count tracks. - 33 - CXD2586R/-1 $8X commands Command Mode specification Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 D0 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 CD- DOUT DOUT VCO VCO WSEL ASHS SOCT ROM Mute Mute-F SEL1 SEL2 C2PO timing See the Timing Chart 1-3 See the Timing Chart 1-3 Processing Command bit CDROM = 1 CDROM = 0 CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing Command bit DOUT Mute = 1 DOUT Mute = 0 When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Command bit D. out Mute F = 1 D. out Mute F = 0 Processing When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DOUT Mute D.out Mute F DOUT output DA output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -dB -dB 0dB 0dB -dB 0dB -dB OFF 0dB See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. - 34 - CXD2586R/-1 Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit ASHS = 0 ASHS = 1 Function The command transfer rate to SSP is set to normal speed. The command transfer rate to SSP is set to half speed. See "4-8. Playback Speed" for settings. Command bit SOCT = 0 SOCT = 1 Sub Q is output from the SQSO pin. Function Each output signal is output from the SQSO pin. Input the readout clock to SQCK. (See the Timing Chart 2-4.) Command bit VCOSEL1 KSL3 KSL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Processing Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to high speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to high speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to high speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to high speed, and the output is 1/8 frequency-divided. Approximately twice the normal speed Command bit VCOSEL2 KSL1 KSL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Processing Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided. Wide-band PLL VCO2 is set to high speed, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to high speed, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to high speed, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to high speed, and the output is 1/8 frequency-divided. Approximately twice the normal speed - 35 - CXD2586R/-1 $9X commands Command Data 1 D3 D2 D1 D0 D3 BiliGL MAIN D2 BiliGL SUB Data 2 D1 FLFC D0 0 Function DCLV DSPB A.SEQ D.PLL specifications ON-OFF ON-OFF ON-OFF ON-OFF Command bit CLV mode In CLVS mode Contents FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0, and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. When DCLV PWM and MD = 1 (Prohibited in CLVW and CAV-W modes) When DCLV PWM and MD = 0 MDS = PWM polarity signal, carrier frequency of 132kHz. MDP = PWM absolute value output (binary), carrier frequency of 132kHz. MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz. DCLV on/off = 0 In CLVP mode DCLV on/off = 1 (FSW, MON not required) In CLVS and CLVP modes When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1. Command bit DSPB = 0 DSPB = 1 Processing Normal-speed playback, C2 error correction quadruple correction. Double-speed playback, C2 error correction double correction. FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. - 36 - CXD2586R/-1 Command bit DPLL = 0 Meaning RFPLL is analog. PDO, VCOI and VCOO are used. DPLL = 1 RFPLL is digital. PDO is high impedance. External parts for the FILI, FILO, PCO pins are required even when analog PLL is selected. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO: The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. Command Function specifications Data 3 D11 DAC EMPH D10 DAC ATT D9 0 D8 0 D7 PLM3 D6 Data 4 D5 PLM1 D4 PLM0 PLM2 The command bits control the DAC. Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel. Command bit DAC EMPH = 1 DAC EMPH = 0 Processing Applies digital de-emphasis. When Fs = 44.1kHz, the emphasis constants are 1 = 50s and 2 = 15s. Turns digital de-emphasis off. Command bit DAC ATT = 1 DAC ATT = 0 Processing Identical digital attenuation control is used for both channels 1 and 2. When common attenuation data is specified, the attenuation values for channel 1 is used. Independent digital attenuation control is used for both channels 1 and 2. * DAC PLAY MODE Command DAC play mode D7 PLM3 D6 PLM2 D5 PLM1 D4 PLM0 By controlling these command bits, the DAC outputs channel 1 and channel 2 can be output in 16 different combinations of left channel, right channel, left + right channel, and mute. The relationship between the commands and the outputs is shown on the table on the following page. - 37 - CXD2586R/-1 PLM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PLM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PLM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PLM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel 1 output Channel 2 output Mute L R L+R Mute L R L+R Mute L R L+R Mute L R L+R Mute Mute Mute Mute L L L L R R R R L+R L+R L+R L+R Remarks Mute Reverse Stereo Mono Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel. The output data of L+R is (L+R)/2 to prevent overflow. - 38 - CXD2586R/-1 $AX commands Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 PCT1 D2 PCT2 Data 2 D1 DADS D0 SOC2 Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off -12dB Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin =1). (4) When GFS stays low for over 35ms (during normal-speed). (5) When register 9 BiliGL MAIN = Sub =1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1 ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain x 0dB x 0dB Mute x 0dB ECC error correction ability C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Description of level meter mode (See the Timing Chart 1-4.) * When the LSI is set to this mode, it performs digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub Q data. (See 2. Subcode Interface.) The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and L/R flag. L/R flag is high when the 15-bit PCM data is from the left channel and low from the right channel. * PCM data is reset zero and the L/R flag is reversed after one readout. Then level measuring continues until the next readout. - 39 - CXD2586R/-1 Description of peak meter mode (See the Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the LSI internal register is set the value again. In other words, the PCM maximum value detection register is not reset to zero by the readout. * To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute. * The Sub Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. * The final bit (L/R flag) of the 96-bit data is normally 0. * The pre-value hold and average value interpolation data are fixed to level (- ) in this mode. Command bit DADS = 0 DADS = 1 Processing Set to 0 when crystal = 33.8688MHz. Set to 1 when crystal = 16.9344MHz. Command bit SOC2 = 0 SOC2 = 1 Processing The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. SENS output switching * This enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. - 40 - CXD2586R/-1 * DAC digital attenuator Command Data 3 D3 D2 D1 D0 D3 Data 4 D2 D1 D0 D3 Data 5 D2 D1 D0 D3 Data 6 D2 D1 D0 Audio AT1D7 AT1D6 AT1D5 AT1D4 AT1D3 AT1D2 AT1D1 AT1D0 AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0 Ctrl Note) AT1D7 to AT1D0 are the channel 1 ATT control bits. AT2D7 to AT2D0 are the channel 2 ATT control bits. Command bits AT1D7 to AT1D0 (AT2D7 to AT2D0) FF (H) FE (H) 01 (H) 00 (H) Audio output 0dB -0.034dB -48.131dB - The attenuation data consists of 8 bits each for channels 1 and 2; the DAC ATT bit can be used to control channels 1 and 2 with common attenuation data. (When common attenuation data is specified, the attenuation values for channel 1 is used.) An attenuation value, from 00(H) to FF(H), is determined according to the following expression: ATT = 20 log [input data/255] dB Example: When the attenuation data is FA(H): ATT = 20 log [250/255] dB = -0.172dB * Soft mute With the soft mute function, when the attenuation data goes from FF(H) to 00(H) and vice versa, muting is turned on and off over the muting time of 1024fs [s] = 23.2 [ms] (Fs = 44.1kHz). * Attenuation Assume the attenuation data ATT1, ATT2, and ATT3, where ATT1 > ATT3 > ATT2. First, assume ATT1 is transferred and then ATT2 is transferred. If ATT2 is transferred before ATT1 is reached (state "A" in the diagram), then the value continues approaching ATT2. Next, if ATT3 is transferred before ATT2 is reached (state "B" or "C" in the diagram), the attenuation begins approaching ATT3 from the current point. Note that it takes 1024/Fs [s] (Fs = 44.1kHz for CD players) to transit between attenuation data (from 0dB to - ). 0dB A ATT1 B ATT3 C ATT2 Handling of the Attenuation Value - 41 - CXD2586R/-1 * I/O sync circuit Related pins: LRCK and XWO During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation proceeds in phase with the serial input data. However, there is a chance that synchronization will not be performed if there is a great deal of jitter in LRCK, if the power has just been turned on, etc. In this case, forced synchronization is possible by setting XWO low for 2/Fs or more. The forced synchronization operation is performed at the second rising edge of LRCK after the XWO pin is set low. $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 Data 2 Data 3 Data 4 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT. - 42 - CXD2586R/-1 $CX commands Command D3 Servo coefficient setting CLV CTRL ($DX) Data 1 D2 D1 D0 D3 Data 2 D2 D1 0 D0 0 Explanation Valid only when DCLV = 1. Valid when DCLV = 1 or 0. Gain Gain Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 Gain CLVS The spindle servo gain is externally set when DCLV = 1. * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB Note) When DCLV = 0, the CLVS gain is as follows. When Gain CLVS = 0, GCLVS = -12dB. When Gain CLVS = 1, GCLVS = 0dB. * CLVP mode gain setting: GMDP, GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV1 0 0 1 Gain DCLV0 0 1 0 GDCLV 0dB +6dB +12dB - 43 - CXD2586R/-1 $DX commands Data 1 Command CLV CTRL D3 DCLV PWM MD D2 TB D1 TP D0 Gain CLVS D3 VP7 Data 2 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 See the $CX commands. Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Explanation Digital CLV PWM mode specified. Both MDS and MDP are used. CLV-W and CAV-W modes can not be used. Digital CLV PWM mode specified. Ternary MDP values are output. CLV-W and CAV-W modes can be used. Explanation Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes. Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. Command bit TB = 0 TB = 1 TP = 0 TP = 1 * For the CXD2586R Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) : VP0 to 7 = C0 (H) : VP0 to 7 = A0 (H) Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at double (quadruple) speed to Playback at (sextuple) speed The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value Note) 1. Values when MCLK is 16.9344MHz and XTSL is low or when MCLK is 33.8688MHz and XTSL is high. 2. Values in parentheses are for when DSPB is 1. 6 5 R -- Relative velocity [times] 4 3 DSPB = 1 2 DSPB = 0 1 F0 E0 D0 VP0 to 7 setting value [HEX] C0 B0 A0 - 44 - CXD2586R/-1 * For the CXD2586R-1 Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) : VP0 to 7 = C0 (H) : VP0 to 7 = A0 (H) : VP0 to 7 = 80 (H) Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at double (quadruple) speed to Playback at triple (sextuple) speed to Playback at (octuple) speed Note) 1. Values when MCLK is 16.9344MHz and XTSL is low or when MCLK is 33.8688MHz and XTSL is high. 2. Values in parentheses are for when DSPB is 1. 8 7 6 R -- Relative velocity [times] 5 4 3 DSPB = 1 2 DSPB = 0 1 F0 E0 D0 C0 VP0 to 7 setting value [HEX] B0 A0 90 80 - 45 - CXD2586R/-1 $EX commands Command SPD mode Data 1 D3 CM3 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode. Explanation Spindle forward rotation mode. Spindle reverse rotation mode. Valid only when LPWR=0, in any modes. Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA See the Timing Charts 1-6 to 1-12. Command bit EPWM SPDC 0 0 0 1 0 0 1 0 ICAP 0 0 1 1 SFSL 0 0 0 0 VC2C 0 1 0 0 HIFC 0 1 1 1 LPWR VPON 0 0 0 0 0 0 1 1 Mode CLV-N CLV-W CAV-W CAV-W Explanation Crystal reference CLV servo. Used for playback in CLV-W mode. Spindle control with VP0 to 7. Spindle control with the external PWM. Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. - 46 - CXD2586R/-1 Mode DCLV DCLV PWM MD LPWR Command KICK Timing chart 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-11 (a) 1-11 (b) 1-11 (c) 1-12 (a) 1-12 (b) 1-12 (c) 0 0 0 BRAKE STOP KICK CLV-N 1 0 0 BRAKE STOP KICK 1 0 BRAKE STOP KICK 0 CLV-W 1 0 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 0 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N DCLV 1 DCLV PWM MD 0 1 0 LPWR 0 0 0 1 0 Timing chart 1-13 1-14 1-15 1-16 1-17 (CAV = 0) 1-18 (CAV = 0) 1-19 (CAV = 1) 1-20 (CAV = 1) CLV-W 1 CAV-W 1 0 1 0 1 Note) The CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 47 - CXD2586R/-1 Command SPD mode Data 4 D3 Gain CAV1 D2 Gain CAV0 D1 FCSW D0 0 Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. Command bit FCSW = 0 FCSW = 1 Processing The VPCO2 pin is not used and it is Hi-Z. The VPCO2 pin is used and the pin signal is the same as VPCO1. - 48 - Timing Chart 1-3 LRCK 48 bit slot WDCK - 49 - Rch 16bit C2 Pointer Lch 16bit C2 Pointer C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer CDROM = 0 If C2 Pointer = 1, data is NG C2PO CDROM=1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD2586R/-1 Timing Chart 1-4 750ns to 120s 80 81 96 1 2 3 SQCK SQSO CRCF D0 15-bit peak-data Absolute value display, LSB first D1 D2 D3 D4 D5 D6 D13 D14 L/R Sub Q Data See "Sub Code Interface" Peak data L/R flag 2 1 2 3 3 - 50 - 96 clock pulses CRCF R/L Peak data of this section 16 bit 1 WFCK 96 clock pulses SQCK SQSO L/R CRCF 96 bit data Hold section Level Meter Timing CXD2586R/-1 Timing Chart 1-5 1 1 2 3 2 3 WFCK 96 clock pulses 96 clock pulses SQCK - 51 - CRCF Measurement CRCF CRCF Measurement Measurement Peak Meter Timing CXD2586R/-1 CXD2586R/-1 Timing Chart 1-6 CLV-N mode DCLV = DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-7 CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP - 52 - CXD2586R/-1 Timing Chart 1-8 CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0 KICK H BRAKE STOP MDS MDS L MDS MDP H MDP L H MDP L L FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-9 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). (b) BRAKE Other than when following the velocity, the timing is the same as Timing Chart 1-6 (b). (c) STOP - 53 - CXD2586R/-1 Timing Chart 1-10 CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Other than when following the velocity, the timing is the same as Timing Chart 1-6 (a). Timing Chart 1-11 CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP - 54 - CXD2586R/-1 Timing Chart 1-12 CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP Z MDP Z FSW L FSW L FSW L MON H MON H MON H (a) KICK (b) BRAKE (c) STOP Timing Chart 1-13 CLV-N mode DCLV PWM MD = LPWR = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Deceleration Z Timing Chart 1-14 CLV-N mode DCLV PWM MD = 1, LPWR = 0 MDS Acceleration MDP 132kHz 7.6s Output Waveforms with DCLV = 1 Deceleration n * 236 (ns) n = 0 to 31 - 55 - CXD2586R/-1 Timing Chart 1-15 CLV-W mode DCLV PWM MD = LPWR = 0 MDS Z Acceleration MDP Z Deceleration Output Waveforms with DCLV = 1 264kHz 3.8s Timing Chart 1-16 CLV-W mode DCLV PWM MD = 0, LPWR = 1 MDS Z Acceleration MDP Z 264kHz 3.8s Output Waveforms with DCLV = 1 The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-17 CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-18 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 56 - CXD2586R/-1 Timing Chart 1-19 CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-20 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. Note) The CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 57 - CXD2586R/-1 2. Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-1.) 2-2. 80-bit Sub Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q has been inputted, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * In the CXD2586R/-1, when 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQSO input is detected, and the retriggerable monostable multivibrator for low is reset. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. * In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit P/S register. Input for ring control 1 is connected to the output of it in peak meter or level meter mode. Same goes for ring 2 in peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result , the 96-bit clock must be input in peak meter mode. * The absolute time after peak is stored in the memory in peak meter mode. (See the Timing Chart 2-3.) * The high and low intervals for SQCK should be between 750ns and 120s. - 58 - CXD2586R/-1 Timing Chart 2-1 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 59 - Block Diagram 2-2 (ASEC) (AMIN) ADDRS CTRL (AFRAM) SUBQ SIN 80 bit S/P Register ABCDEFGH 8 Order Inversion 8 8 8 8 8 8 8 8 HG F EDC B A 80 bit P/S Register SI SO LD LD LD LD LD LD LD SUBQ LD - 60 - CRCC Monostable multivibrator SHIFT LOAD CONTROL SO 16 bit P/S register SI 16 Peak detection ABS time load control for peak value SHIFT SQCK Ring control 1 Ring control 2 CRCF Mix SQSO CXD2586R/-1 Timing Chart 2-3 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK SCOR Determined by mode CRCF1 80 or 96 Clock CRCF2 SQSO CRCF1 SQCK Register load forbidder - 61 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Monostable Multivibrator (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2586R/-1 Timing Chart 2-4 Example: $8020 latch Set SQCK high during this interval. XLAT 750ns or more Internal signal latch SQCK SQSO PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH ALOCK VF0 VF1 VF2 VF3 PER0 PER1 PER2 PER3 VF4 VF5 VF6 VF7 Signal Explanation PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK GFS High when the frame sync and the insertion protection timing match. LOCK High when sampled value of GFS at 460Hz is high. Low when sampled value of GFS at 460Hz is low by 8 times successively. - 62 - Description ; C1 pointer reset C2F2 0 0 0 0 ; C1 pointer set 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 -- -- EMPH High when the playback disc has emphasis. ALOCK High when sampled value of GFS at 460Hz is high by 8 times successively. Low when sampled value of GFS at 460Hz is low by 8 times successively. VF0 to 7 Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See the Timing Chart 2-5.) VF0 = LSB, VF7 = MSB. Description No C2 errors One C2 error corrected ; C2 pointer reset ; C2 pointer reset Two C2 errors corrected ; C2 pointer reset Three C2 errors corrected; C2 pointer reset -- Four C2 errors corrected ; C2 pointer reset C2 correction impossible ; C1 pointer copy C2 correction impossible ; C2 pointer set C1F2 C1F1 C1F0 0 0 0 No C1 errors 0 0 1 One C1 error corrected ; C1 pointer reset 0 1 0 0 1 1 1 0 0 No C1 errors 1 0 1 One C1 error corrected ; C1 pointer set CXD2586R/-1 1 1 0 Two C1 errors corrected ; C1 pointer set 1 1 1 C1 correction impossible ; C1 pointer set CXD2586R/-1 Timing Chart 2-5 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load VF0 to 7 m The relative velocity of the disc can be obtained with the following equation. R= m+1 (R: Relative velocity, m: Measurement results) 32 VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from MCLK (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 63 - CXD2586R/-1 3. Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2500 series, and operation is the same (however, variable pitch cannot be used). The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the CXD2500 series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the lowpass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the VCKI pin.) While starting to rotate a disc and/or speeding up to the lock range from the condition that a disc stops, CAV-W mode should be used. Concretely saying, firstly send $E665X to set CAV-W mode and kick a disc, secondly send $E60CX to set CLV-W mode if ALOCK is high, which can be read serially from SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return to adjust speed operation (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode, set DCLV PWM MD to low. Note) The capture range for this mode is theoretically up to the signal processing limit. 3-3. CAV-W Mode This is the CAV mode. In this mode, it is possible to control spindle to variable rotational velocity, the external crystal is fixed though. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting the CAV-W mode with $E665X command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to sextuple-speed. (See $DX Commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. And the reference for the velocity measurement is a signal of 132.2kHz obtained by 1/128 of MCLK (384Fs). The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8 bits (VP0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256-n for control with VP0 to 7. (See Table 2-5 and Fig. 26.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode. - 64 - CXD2586R/-1 CAV-W Rotational velocity CLVS Target velocity CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to regular playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CAV-W $E6C00 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart - 65 - CXD2586R/-1 4. Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is needed to demodulate the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. Practically, PLL is necessary to regenerate the channel clock, because the EFM pulse width is altered by spindle rotation fluctuation. The block diagram of this PLL is shown in Fig. 4-1. The CXD2586R/-1 has a built-in three-stage PLL. * The first-stage PLL is for the wide-band PLL. When the built-in VCO2 is used, LPF is required externally. When the built-in VCO2 is not used, LPF and VCO are required externally. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL generates a high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock. * The digital PLL in CLV-N mode has a secondary loop, which is the primary loop (phases) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High-frequency components such as 3T and 4T may contain deviations. In such a case, turning the secondary loop off yields better playability. However, in this case the capture range becomes 50kHz. * The new digital PLL in CLV-W mode follows the rotational velocity of the disc, in addition to the abovementioned secondary loop. - 66 - CXD2586R/-1 Block Diagram 4-1 CLV-W CAV-W Spindle rotation information Selector Clock input 1/2 MCLK XTSL 1/32 VPCO1 to 2 Phase comparator CLV-N 1/2 1/n CLV-W CAV-W /CLV-N Microcomputer control n = 1 to 256 (VP7 to 0) LPF VCOSEL2 1/K (KSL1, 0) VCTL VCO2 V16M 2/1 MUX VPON VCKI Phase comparator 1/M PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL CXD2586 VCOSEL1 - 67 - CXD2586R/-1 4-2. Frame Sync Protection * In normal speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2586R/-1, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync has been played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If frame sync cannot be detected for 13 frames or more, the window is released and try to resyncronize the frame sync. In addition, immediately after the window is released and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window is released immediately. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD2586R/-1 uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. * The correction status can be monitored externally. See the Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible C2 correction impossible Table 4-2. - 68 - No C1 errors One C1 error corrected Two C1 errors corrected C1 correction impossible No C2 errors One C2 error corrected Two C2 errors corrected No C1 errors One C1 error corrected Description ; C1 pointer reset ; C1 pointer reset -- -- ; C1 pointer set ; C1 pointer set ; C1 pointer set ; C1 pointer set ; C2 pointer reset ; C2 pointer reset ; C2 pointer reset Three C2 errors corrected ; C2 pointer reset Four C2 errors corrected ; C2 pointer reset -- ; C1 pointer copy ; C2 pointer set CXD2586R/-1 Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 4-4. DA Interface * The CXD2586R/-1 has two modes as DA interfaces. a) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. - 69 - Timing Chart 4-4 48bit slot Normal-Speed Playback PSSL = L LRCK (44.1K) 6 7 8 9 10 11 12 24 1 2 3 4 5 DA15 (2.12M) WDCK DA16 L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB - 70 - 24 L0 Rch MSB 48bit slot Double-Speed Playback LRCK (88.2K) 12 DA15 (4.23M) WDCK DA16 R0 Lch MSB (15) CXD2586R/-1 Timing Chart 4-5 64 Bit slot Normal Speed PB PSSL = L DA12 (44.1K) 8 9 10 11 12 13 14 15 20 30 31 32 1 2 3 4 5 6 7 DA13 (2.82M) DA14 R ch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 L ch LSB (0) - 71 - 10 15 20 25 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L ch LSB 64 Bit slot Double- Speed PB DA12 (88.2K) 1 2 3 4 5 DA13 (5.64M) DA14 R ch LSB (0) L15 CXD2586R/-1 CXD2586R/-1 4-5. Digital Out There are three digital output formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CDX2586R/-1 supports type 2 form 1. In addition, regarding the clock accuracy of the channel status, level II is set for crystal clock use and level III for CAV-W mode. In addition, Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode. Therefore, set MD2 to 0 and turn DOUT off. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 bit0 to 3 bit29 Sub Q control bits that matched twice with CRCOK VPON: 1 Crystal: 0 Table 4-6. - 72 - CXD2586R/-1 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, fine search, and M track move are executed automatically. Servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the servo, but can be sent to the CXD2586R/-1. In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built in this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See 1, $4X commands concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking and sled servo are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-9. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set in register 5), the tracking and sled servos are turned on. - 73 - CXD2586R/-1 * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-11. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-12. The differences from a 2N-track jump are a higher precision jump achieved by controlling the traverse speed and a longer distance jump achieved by controlling the sled. The track jump count is set in register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F in register 6 and overflow G in register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls in register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set in register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N- for the traverse monitor counter which is set in register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. * M track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M track move is performed in accordance with Fig. 4-13. M can be set to 216 tracks. COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servo are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 after the actuator is stabled. - 74 - CXD2586R/-1 Auto focus Focus search up FOK = H YES NO FZC = H YES NO Check whether FZC is continuously high for the period of time E set with register 5. FZC = L YES Focus servo ON NO END Fig. 4-8 (a). Auto Focus Flow Chart $47 Latch XLAT FOK SEIN (FZC) BUSY Command for SSP $03 Blind E $08 Fig. 4-8 (b). Auto Focus Timing Chart - 75 - CXD2586R/-1 1 Track Track kick sled servo WAIT (Blind A) REV kick for REV jump COUT = YES Track REV kick WAIT (Brake B) Track sled servo ON NO FWD kick for REV jump END Fig. 4-9 (a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 4-9 (b). 1-Track Jump Timing Chart - 76 - CXD2586R/-1 10 Track Track, sled FWD kick WAIT (Blind A) (Counts CNIN x 5) COUT = 5 ? NO YES Track, REV kick Check whether the CNIN cycle is longer than overflow C. C = Over-flow ? NO YES Track, sled servo ON END Fig. 4-10 (a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A Command for SSP COUT 5 count Over-flow C $2A ($2F) $2E ($2B) $25 Fig. 4-10 (b). 10-Track Jump Timing Chart - 77 - CXD2586R/-1 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N Counts COUT for the first 16 times and MIRR for more times NO YES Track REV kick C = Over-flow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 4-11 (a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for SSP $2A ($2F) COUT (MIRR) N count $2E ($2B) Over-flow C $26 ($27) Kick D $25 Fig. 4-11 (b). 2N Track Jump Timing Chart - 78 - CXD2586R/-1 Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Over-flow G) COUT = N ? NO YES Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-12 (a). Fine Search Flow Chart $44 (REV = $45) latch XLAT COUT BUSY Kick D $26 ($27) Kick F Traverse Speed Control (Overflow G) & COUT N count Kick D $27 ($26) $25 $2A ($2F) Fig. 4-12 (b). Fine Search Timing Chart - 79 - CXD2586R/-1 M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) COUT (MIRR) = M Counts CNIN till M < 16. Counts MIRR till M 16. NO YES Track, Sled Servo ON END Fig. 4-13 (a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for servo $22 ($23) COUT (MIRR) M count $20 Fig. 4-13 (b). M-Track Move Timing Chart - 80 - CXD2586R/-1 4-7. Digital CLV Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, sampling frequency is 130Hz at most during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 Mux Gain MDS + Gain DCLV Over Sampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI DCLVMD, LPWR Mode Select MDS MDP CLVS U/D: MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer Fig. 4-14. Block Diagram - 81 - CXD2586R/-1 4-8. Playback Speed In the CXD2586R/-1, the following playback modes can be selected through different combinations of MCLK, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency dividing command (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. * For the CXD2586R/-1 Mode 1 2 3 4 5 6 7 8 9 10 11 MCLK 1152Fs 1152Fs 1152Fs 1152Fs 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 0 1 0 1 1 VCOSEL11 0/1 1 1 1 0/1 0/1 1 1 0/1 0/1 0/1 ASHS 1 1 2 2 0 0 1 1 0 0 0 Playback speed x 1.5 x3 x3 x6 x1 x2 x2 x4 x1 x2 x1 Error correction C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, use the optimal value by combining KSL3 with KSL2. 2 The built-in auto sequencer can not be used. The playback speed can be varied by setting VP0 to 7 in CAV-W mode. See "3. Description of Modes" for details. - 82 - CXD2586R/-1 4-9. DAC Block Playback Conditions * The DAC block playback speed is controlled by sending the DADS command to the DSP block. Mode 1 2 X'tal 768fs 384fs DADS 0 1 4-10. DAC Block Input Timing The timing charts for input to the DAC are shown below. In the CXD2586R/-1, audio data is not sent from the CD signal processor block to the DAC block inside the LSI. The reason why is to allow data to be passed through an audio DSP, etc., on its way to the DAC block. To input data to the DAC block without passing it through an audio DSP, etc., the data connection must be made externally. In this case, LRCK, BCK, and PCMD can be connected directly to LRCKI, BCKI, and PCMDI. (See the Application Circuit.) Normal-speed Playback LRCKI (44.1k) 1 BCKI (2.12M) PCMDI Invalid L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 - 83 - CXD2586R/-1 LPF Block The CXD2586R/-1 contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD - AVSS)/2. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc 40kHz. The capacitance of the external capacitors when fc = 30kHz and 50kHz are noted below as a reference. * When fc 30kHz: C1 = 200pF, C2 = 910pF * When fc 50kHz: C1 = 120pF, C2 = 560pF LPF Block Application Circuit AOUT1 58 12k C2 680p VC AIN1 57 12k 12k C1 150p LOUT1 56 Analog out LPF external circuit - 84 - CXD2586R/-1 4-11. CXD2586R/-1 Clock System The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below; during normal use, MCKO and MCLK are directly connected to each other, and FSTO and FSTI are directly connected to each other. XTLI 384fs or 768fs XTLO OSC 1/2 Clock supplied to DAC 384fs To DAC block DADS (command register) MCKO External connection MCLK 1/2 XTSL To digital signal processor block 2/3 FSTO External connection FSTI 1/2 128fs To digital servo block 1/4 XT2D XT4D (command register) - 85 - CXD2586R/-1 [5] Description of Servo Signal Processing-System Functions and Commands 5-1. General Description of the Servo Signal Processing System (Voltages are the values for a 5V power supply.) Focus servo Sampling rate: 88.2kHz Input range: 2.5V center 1.0V Output format: 7-bit PWM Others: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Automatic gain control Tracking servo Sampling rate: Input range: Output format: Others: 88.2kHz 2.5V center 1.0V 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Automatic gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Others: 345Hz 2.5V center 1.0V 7-bit PWM Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz Input range: 2.15V to 5.0V Others: RF zero level automatic measurement The signal input from the RFDC pin is multiplied by a factor of 0.7 and loaded into the A/D converter. - 86 - CXD2586R/-1 5-2. Digital Servo Block Master Clock (MCK) The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The frequency division ratio is 1/2 or 1/4. Table 3-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin. The XT4D and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz. Mode MCLK FSTO 1 2 3 4 384Fs 256Fs 384Fs 256Fs 768Fs 512Fs 768Fs 512Fs FSTI 256Fs 256Fs 512Fs 512Fs XTSL 0 1 XT4D 0 0 1 0 XT2D 1 0 0 0 Frequency division ratio 1/2 1/2 1/4 1/4 MCK frequency 128Fs 128Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 5-1. 5-3. AVRG (Average) Measurement and Compensation The CXD2586R/-1 has a circuit that measures AVRG of RFDC, VC, FE, and TE and a circuit that compensates them to control servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2586R/-1, and is able to cancel the offset by performing each AVRG measurement before playback operation and using these results for compensation. The level applied to the VC, FE RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the average of 256 samples, and then loading these values into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received. During AVRG measurement, if the upper 8 bits of the serial command are 38 (Hex), the completion of AVRG measurement operation can be confirmed through the SENS pin. (See the Timing Chart 5-2.) XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s Completion of AVRG measurement Timing Chart 5-2. - 87 - CXD2586R/-1 - 88 - CXD2586R/-1 5-4. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be adjusted. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 3-3.) When the FBIAS register value is set to D11 = 0 and D10 = 1 by $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SCOT command of $8 to 1. (See the DSP Block Timing Chart.) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. It works as an up/down counter. The FBIAS register works as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and 10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to 1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the serial command are $3A at this time, the counter stop can be monitored through SENS. Here, the FBIAS setting values FB9 to 1 and the FBIAS LIMIT values FBL9 to 1 are assumed to be set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter changes with each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to approximately 3.9 [mV]. A: Register mode B: Counter mode C: Counter mode (when stopped) A B C FBIAS setting value (FB9 to 1) LIMIT value (FBL9 to 1) SENS pin - 89 - RFDC from A/D RF AVRG register RFLC - To RF In register TE, SE from A/D - TLC0 - - To TRK/SLD In register VC AVRG register TLC1 TLC2 TE AVRG register TRVSC register - 90 - VCLC - FE AVRG register FLC1 - FBIAS register FBON FLC0 - FE from A/D To FCS In register + To FZC register CXD2586R/-1 Fig. 5-3. CXD2586R/-1 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the serial command are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See the Timing Chart 5-4 and the Description of SENS Signals.) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL termination Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 changes for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has terminated, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related setting The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during high sensitivity adjustment) AGV2; AGCNTL sensitivity 2 (during low sensitivity adjustment) AGHS; High sensitivity adjustment on/off AGHT; High sensitivity adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 91 - CXD2586R/-1 AGCNTL and default operation have two stages. In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with AGHT), and the AGCNTL coefficient approaches the appropriate value roughly. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient approaches the appropriate value finely with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2586R/-1 confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ), and then terminates AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the various settings are shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL start SENS AGJ AGCNTL completion Fig. 5-5. - 92 - CXD2586R/-1 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 93 - CXD2586R/-1 5-8. TRK (Tracking) and SLD (Sled) Servo Control TRK and SLD servo is controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial command are 2 (Hex), TZC is output from the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 5-9. 2 TRACKING MODE 0010 TRK Servo The TRK JUMP (track jump) height can be set with the 6 bits D13 to D8 of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter assumes gain-up status. The TRK servo filter also assumes gain-up status when vibration detection is performed with the LOCK signal low and the anti-shock circuit (described hereafter) enabled. The gain-up filter used when TRK has assumed gain-up status has two types of structures which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from the 6 bits D13 to D8 of $37, is determined by multiplying this value by x 1, x 2, x 3, or x 4 magnification set using D17 and D16 when D19 = D18 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50 s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo is set gain-up status and the SLD servo is turned off, by the default. This is disabled by setting D6 (LKSW) of $38 to 1. Register name Command D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) D23 to D20 Table 5-10. - 94 - CXD2586R/-1 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of these envelope waveforms. The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by subtracting the bottom hold value from the peak hold value. (See Fig. 5-11.) RF Peak Hold Bottom Hold Peak Hold -Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 -Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. - 95 - CXD2586R/-1 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit performs operations to maintain the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by performing scratch and defect detection with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1 or by inputting high level to the DFSW pin. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 5-13. 5-11. Anti-Shock Circuit When vibrations are produced in the CD player, this circuit forces the TRK filter to assume gain-up status so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can also set the TRK servo filter to gain-up status by inputting high level to the ATSK pin. When the serial command is $1, vibration detection can be monitored from the SENS pin. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen Fig. 5-14. - 96 - CXD2586R/-1 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, this circuit cuts unnecessary portions of the tracking drive and works it as the brake by utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) Inner track Outer track Outer track Inner track FWD REV Servo ON JMP JMP TRK DRV TRK DRV REV FWD Servo ON JMP JMP RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 Fig. 5-15. Register name Fig. 5-16. Command D23 to D20 D19 to D16 10 0 1 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Fig. 5-17. - 97 - 1 TRACKING CONTROL 0001 CXD2586R/-1 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and there are two types of output methods according to the COUT signal application. for 1-track jumps, etc. Fast phase COUT signal with a fast phase TZC signal. for High-speed traverse Reliable COUT signal with a delayed phase TZC signal. This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3. (When D16 = 1, for delayed phase and high-speed traverse.) In addition, the TZC signal delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and the Description of SENS Signals.) Specified commands $390C VC AVRG measurement result $3908 FE AVRG measurement result $3904 TE AVRG measurement result $391F RF AVRG measurement result $3953 FCS AGCNTL coefficient result $3963 TRK AGCNTL coefficient result $391C TRVSC adjustment result $391D FBIAS register value XLAT tDLS tSPW SCLK 1/fSCLK *** Serial Read Out Data (SENS) MSB *** LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 1 500 15 Unit MHz ns s tSPW tDLS Table 5-19. During readout, the upper 8 bits of the serial data must be 39 (Hex). - 98 - CXD2586R/-1 5-15. Writing the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. 5-16. PWM Output FCS, TRK and SLD outputs are output as PWM waveforms. In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper. Timing Chart 5-20 and Figs. 5-21 and 5-22 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK SFON SFDR SRON SRDR 1tMCK AtMCK AtMCK 1tMCK 64tMCK 64tMCK Output value -A Output value 0 FCS/TRK 32tMCK FFON/ TFON FFDR/ TFDR FRON/ TRON FRDR/ TRDR 1tMCK A tMCK 2 1tMCK A tMCK 2 1tMCK A tMCK 2 A tMCK 2 1tMCK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK The ON signal (FON and RON) is active low. tMCK = 1 180ns 5.6448MHz Timing Chart 5-20. - 99 - CXD2586R/-1 Example of Driver Circuits VDD FON DRV+ DRV- RON RDR FDR GND Fig. 5-21. PWM Bridge Drive Circuit VCC 22k 22k RDR FDR 22k 22k DRV VEE Fig. 5-22. Operational Amplifier Drive Circuit - 100 - CXD2586R/-1 5-17. DIRC Input Pin The $2 command register can be changed by operating the DIRC input pin. Using the DIRC pin allows serial data transfer to be simplified during TRKJMP. Fig. 5-23 shows $2 command register changes produced by DIRC pin changes. In addition, Timing Chart 5-24 shows DIRC-based operations during TRKJMP. High level must be input to the DIRC pin when the XRST pin rises from low to high. DIRC Q3 0 TRK 0 1 1 Q2 0 1 0 1 Servo status OFF ON FWD JMP REV JMP Q3 1 1 1 1 Q2 1 0 1 0 Servo status REV JMP FWD JMP REV JMP FWD JMP Q3 0 0 0 0 Q2 1 1 1 1 Servo status ON ON ON ON Q1 0 SLD 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 0 1 0 1 Servo status OFF ON FWD MOV REV MOV Q1 0 0 1 1 Q0 1 1 0 1 Servo status ON ON FWD MOV REV MOV Q3, Q2, Q1 and Q0 correspond to D19, D18, D17 and D16 of $2. Fig. 5-23. $28 latch $2C latch XLAT DIRC ON FWD JUMP REV JUMP TRK SERVO SLD SERVO OFF ON OFF ON OFF ON OFF Timing Chart 5-24. - 101 - CXD2586R/-1 5-18. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo assumes the gain-up status and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 5-19. Description of Commands and Data Sets The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. Both types of conversion are calculated at VDD = 5.0V. If this voltage changes, the conversion values also change proportionally. (Voltage conversion = VDDX/5; VDDX: used supply voltage) - 102 - CXD2586R/-1 $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0 KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to 1 matches FBL9 to 1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data. For FE input conversion, FB9 to FB1 = 011111111 corresponds to approximately +1V and FB9 to FB1 = 100000000 to -1V respectively. (when the supply voltage = 5V) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 1 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to approximately +1V and TV9 to TV0 = 1100000000 to -1V respectively. (when the supply voltage = 5V) Note) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit of TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 103 - CXD2586R/-1 $35 D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (3.36V/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed 6.73 V/s 3.36 2.24 1.68 8.97 5.38 4.49 3.85 FS5 to FS0: FG6 to FG0: Focus search limit voltage Default value: 011000 (1.875V) Focus drive output conversion AGF convergence gain setting value Default value: 0101101 $36 D15 0 DTZC: TJ5 to TJ0: D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 DTZC TJ5 TJ0 SFJP TG6 SFJP: TG6 to TG0: DTZC delay (8.5/4.25s) Default value: 0 (4.25s) Track jump voltage Default value: 001110 ( 1.09V) Tracking drive output conversion Surf jump mode on/off TRK PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on). AGT convergence gain setting value Default value: 0101110 - 104 - CXD2586R/-1 $37 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value:01 (250mV); FE input conversion FZSH 0 0 1 1 SM5 to SM0: FZSL 0 1 0 1 Slice level +500mV +250 +125 +62.5 Sled move voltage Default value: 010000 ( 1.25V) Sled drive output conversion AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1 (large) 0 (small) 1 (large) 63mV 125 125mV 250 AGS: AGJ: AGGF: AGGT: AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms) Default value: 0 (256ms) - 105 - CXD2586R/-1 $38 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VCLC: FLM: FLC0: RFLM: RFLC: AGF: AGT: DFSW: LKSW: TBLM: TCLM: FLC1: TLC2: TLC1: TLC0: VC level measurement (on/off) VC level compensation for FCS In register (on/off) Focus zero level measurement (on/off) Focus zero level compensation for FZC register (on/off) RF zero level measurement (on/off) RF zero level compensation (on/off) Focus automatic gain adjustment (on/off) Tracking automatic gain adjustment (on/off) Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. Lock switch (on/off) Setting this switch to 1 disables the sled free-running prevention circuit. Traverse center measurement (on/off) Tracking zero level measurement (on/off) Focus zero level compensation for FCS In register (on/off) Traverse center compensation (on/off) Tracking zero level compensation (on/off) VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. All commands are on when set to 1. - 106 - CXD2586R/-1 $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: SD6 to SD0: SD6 1 0 Serial data readout DAC mode (on/off) Serial readout data select SD5 Readout data Readout data length 8 bits 16 bits Address = coefficient RAM data for (SD5 to SD0) 1 Address = Data RAM data for (SD4 to SD0) SD4 SD3 to SD0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 0 Note) Coefficients K40 to K4F cannot be read out. : Don't care See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data. - 107 - CXD2586R/-1 $3A D15 0 FBON: D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting D14 to 1 (on). FBSS: FBIAS (focus bias) register/counter switching The FCS BIAS register can be used as a counter by setting D13 to 1 (on). FBUP: FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. The FBIAS register functions as a down counter when D12 is set to 0, and as an up counter when set to 1. FBV1, FBV0: FBIAS (focus bias) counter voltage switching FCS BIAS count up steps is decided by these bits. FBV1 0 0 1 1 FBV0 0 1 0 1 Number of steps 1 2 4 8 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 3.9 [mV]. TJD0: This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. This is effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus (tracking) by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 CEIT: SJHD: INBK: FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB MTI0: The CE pin input takes over the TE pin input by setting D3 to 1 (on). This means that the registers and filters for TE input are used for CE input. This holds the tracking filter output at the value when surf jump starts during surf jump. When D1 is 0 (off), the brake circuit masks the tracking filter output signal with the TRKCNCL which is generated by taking the MIRR signal at the TZC edge. When D1 is set to 1 (on), the tracking filter input is masked instead of the output. The tracking filter input is masked when the MIRR signal is high by setting D0 to 1 (on). - 108 - CXD2586R/-1 $3B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (313mV) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 179mV 223 268 313 357 446 536 625 - 109 - CXD2586R/-1 SDF2,SDF1: DFCT slice level Default value: 10 (179mV) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 89mV 134 179 224 MAX2, MAX1: DFCT maximum time Default value: 00 (no timer limit) MAX2 0 0 1 1 BTF: MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.492V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 0 0 1 1 D2V1 0 1 0 1 Count-down speed [V/ms] 0.246 0.492 0.984 1.969 [kHz] 22.05 44.1 88.2 176.4 D1V2, D1V1: Peak hold 1 for DFCT signal generation Count down speed setting Default value: 01 (3.938V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2 0 0 1 1 RINT: D1V1 0 1 0 1 Count-down speed [V/ms] 1.969 3.938 7.875 15.75 [kHz] 176.4 352.8 705.6 1411.2 This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. - 110 - CXD2586R/-1 $3E D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 D3 0 D2 0 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See FILTER Composition at the end of this specification concerning quasi double-accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when set to 1; default = 0 This command passes the signal obtained from the RFDC pin through the LPF (low pass filter) before the built-in A/D converter. 0: LPF off; default 1: LPF on MIRR input switching. The MIRR signal can be input from an external source. When D1 is 0, the MIRR signal is used internally as usual. When D1 = 1, the MIRR signal can be input from an external source through the MIRR pin. The clock input from FSTI can be used as the master clock for the servo block regardless of the XTSL pin, XT2D and XT4D by setting D0 to 1. TLCD: RFLP: MIRI: XT1D: - 111 - CXD2586R/-1 $3F D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 ASFG D5 0 D4 D3 D2 D1 D0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 LPAS SRO1 SRO0 AGHF COT2 This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. These settings are the same AGGF (MSB) AGGT (LSB) TE/FE input conversion as for both focus auto gain 0 0 31 [mV] control and tracking auto gain 0 1 63 [mV] control. 1 0 125 [mV] 1 1 250 [mV] XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/2 or 1/4 when MCK is generated from the signal input to the FSTI pin. XT4D 0 0 1 XT2D 0 1 0 Frequency division ratio According to XTSL (default) 1/2 1/4 DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when set to 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is set to gain normal status. On when set to 1; default = 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, firstly check whether each error signal is properly A/D converted using the SRO1 and SRO0 commands of $3F. SRO1, SRO0: These commands are to output various data externally continuously which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output can be obtained from three specified pins (SOCK, XOLT and SOUT) by setting these commands to 1 respectively. The default is 0, 0. The output pins for each case are shown below. SRO1 = 1 SOCK XOLT SOUT DA13 DA12 DA14 SRO0 = 1 DA10 DA09 DA11 (See the Description of Data Readout on the following page.) AGHF: COT2: This halves the frequency of the internally generated sine wave during AGC. The STZC signal is output from COUT by setting D0 to 1. (STZC: TZC signal generated by sampling the TE signal at 700kHz) - 112 - CXD2586R/-1 Description of Data Readout SOCK (5.6448MHz) XOLT (88.2kHz) *** *** *** *** SOUT MSB *** LSB MSB *** LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * To the 7-segment LED MSB SOCK CLK CLK Data is connected to the 7-segment LED by 4-bits at a time. This enable Hex display using four 7-segment LEDs. XOLT MSB * SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 113 - CXD2586R/-1 5-20. List of Servo Filter Coefficients - 114 - CXD2586R/-1 Fix indicates that normal preset values should be used. - 115 - CXD2586R/-1 5-21. FILTER Composition The internal filter composition is shown below. K and M indicate coefficient RAM and Data RAM address values respectively. FCS Servo Gain Normal; fs = 88.2kHz FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 DFCT K06 AGFON K06 K0F M03 Z-1 K08 K09 M04 Z-1 K0A 2-7 K0B 2-7 K0D K0C M05 Z-1 K0E FCS Hold Reg 1 M06 Z-1 K10 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K0B and K0D coefficients to 0. FCS Servo Gain Down; fs = 88.2kHz FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 K24 K25 M04 Z-1 K26 2-7 K27 2-7 K29 K28 M05 Z-1 K2A FCS Hold Reg 1 M06 Z-1 K2C K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K27 and K29 coefficients to 0. - 116 - CXD2586R/-1 TRK Servo Gain Normal; fs = 88.2kHz TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K1C 2-7 K1D 2-7 K1F TRK JMP K1E M0D Z-1 K20 K21 M0E Z-1 K22 M0F K23 27 TRK PWM Note) Set the MSB bit of the K1D and K1F coefficients to 0. TRK Servo Gain Up 1; fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K3C K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM - 117 - CXD2586R/-1 TRK Servo Gain Up 2; fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K36 K37 M0C Z-1 K38 2-7 K39 2-7 K3B TRK JMP K3A M0D Z-1 K3C M0E Z-1 K3D K3E M0F K23 27 TRK PWM Note) Set the MSB bit of the K39 and K3B coefficients to 0. SLD Servo; fs = 345Hz TRK AUTO Gain 2-1 SLD In Reg K00 M00 Z-1 K01 2-7 K02 2-7 K04 K03 M01 Z-1 SLD MOV K05 M02 27 K07 SLD PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain; fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 118 - CXD2586R/-1 Anti Shock; fs = 88.2kHz TRK In Reg 2-1 K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG; fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold; fs = 345Hz 2-1 K40 SLD In Reg M18 Z-1 K41 2-7 K42 2-7 M19 Z-1 K43 K45 TRK Hold Reg K44 Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold; fs = 345Hz FCS Hold Reg 1 K48 M10 Z-1 K49 2-7 K4A 2-7 M11 Z-1 K4B K4D FCS Hold Reg 2 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 119 - CXD2586R/-1 FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 AGFON K06 DFCT K06 K0F M03 Z-1 81H 2-7 K08 2-7 K09 K0B 7FH K0A 2-7 2-7 K0D K0E K0C 80H M04 Z-1 M05 Z-1 FCS Hold Reg 1 M06 Z-1 K10 2-7 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 81H 2-7 K24 2-7 K25 K27 7FH K26 2-7 2-7 K29 K2A K28 M04 Z-1 M05 Z-1 80H FCS Hold Reg 1 M06 Z-1 K2C 2-7 K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. - 120 - CXD2586R/-1 TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K1D 7FH K1C 2-7 2-7 K1F K20 TRK JMP K1E M0C Z-1 M0D Z-1 80H 2-7 K21 27 TRK PWM M0E Z-1 K22 M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo Gain up 1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K3C 7FH M0C Z-1 80H 2-7 K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. - 121 - CXD2586R/-1 TRK Servo Gain up 2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K36 2-7 K37 K39 7FH K38 2-7 2-7 K3B K3C TRK JMP K3A M0C Z-1 M0D Z-1 80H 2-7 K3D 27 TRK PWM M0E Z-1 K3E M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. - 122 - CXD2586R/-1 5-22. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 180 G-Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 f-Frequency [Hz] 1K -180 20K FOCUS frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f-Frequency [Hz] 1K -180 20K - 123 - -Phase [degree] G-Gain [dB] -Phase [degree] VDD GFS GND FOK MD2 FSTO FSTI MCLK XTSL 72 DAS1 71 DAS0 70 XWO 69 DTS7 68 DTS6 67 DTS5 66 DTS4 65 DTS3 64 DTS2 63 DTS1 62 NC. 61 AVSS32 60 AVDD3 59 AOUT1 58 AIN1 57 LOUT1 56 AVSS31 55 AVSS5 54 XTLI 53 XTLO 52 AVDD5 51 AVSS42 50 LOUT2 49 AIN2 48 AOUT2 47 AVDD4 46 AVSS41 45 NC. 44 DVSS1 43 DA01 42 DA02 41 DA03 40 DA04 39 DA05 38 DA06 37 XRAOF C2PO MNT0 MNT1 MNT2 MNT3 GND DA08 GFS XRAOF DA07 SCLK XLAT DATA XRST PWMI CLOK SENS MUTE SQCK VC SCOR SQSO WFCK MON SBSO MIRR FSW DFCT COUT EXCK 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC. FOK NC. MON FSW XLAT DFCT MIRR ATSK SCLK DIRC XRST EXCK MD2 PWMI DATA CLOK SENS COUT SQCK SBSO SCOR MUTE DFSW SQSO DVDD2 WFCK DVSS2 DOUT C16M C4M TESTA MCKO 109 NC. 110 MDP MDS 111 112 LOCK 113 SSTP 114 SFDR 115 SRON SRDR SFON 116 117 118 TFDR 119 TRON 120 TRDR 121 TFON 122 123 FRON 124 FRDR 125 FFON 126 DVDD3 127 VCOO 128 VCOI 129 TEST 130 DVSS3 131 TES2 TES3 132 133 NC. 134 PDO 135 VCKI 136 V16M 137 AVDD2 138 IGEN 139 140 ADIO 141 142 RFDC 143 CE 144 TE VPCO2 VC PCO CLTV AVSS1 FE VPCO1 SE BIAS AVDD1 VCTL FILO RFAC ASYI FILI ASYO LRCK DA14 DVDD1 WDCK BCKI DA13 RFC AVSS2 FFDR +5V LOCK SSTP SLED SPDL GND FG TD TG FD Driver circuit LDON PDO VCC GND V16M RFO FZC FE ADIO TE CE VC NC. DOUT C16M PSSL PCMDI DA15 DA11 C4M LDON ASYE LRCKI DA16 NC. DA12 1 2 3 7 4 8 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VC SOUT XOLT SOCK WDCK GTOP XUGF DA10 XPLCK DA09 XWO 6-1. Application Circuit - 124 - CXD2586R/-1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2586R/-1 Package Outline Unit: mm LQFP-144P-L01 144PIN LQFP (PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 72 B A 144 37 1 36 0.5 0.22 0.05 0.1 M S S 0.1 0.05 0.22 0.05 0.1 S (21.0) 0 to 10 DETAIL A 0.5 0.15 0.145 0.05 (0.2) (0.125) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 1.3 g SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT LQFP-144P-L021 144PIN LQFP(PLASTIC) 22.0 } 0.2 20.0 } 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.22 0.05 36 0.1 M S S 0.1 0.05 0.1 S 37 0.5 0.15 (21.0) 0.22 0.05 (0.125) (0.2) 0 to 10 DETAIL A DETAIL B 0.145 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L021 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 125 - CXD2586R/-1 LQFP-144P-L022 144PIN LQFP(PLASTIC) 22.0 } 0.2 20.0 } 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.22 0.05 36 0.1 M S S 0.1 S 37 (21.0) 0.1 0.05 0.22 0.05 (0.125) (0.2) 0 to 10 DETAIL A 0.5 } 0.15 DETAIL B 0.145 0.05 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L022 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 1.3g LQFP-144P-L081 144PIN LQFP(PLASTIC) 22.0 } 0.2 20.0 } 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.1 0.05 0.22 0.05 36 0.1 M S S 0.1 S 37 (21.0) 0.22 0.05 0.5 0.2 0 to 10 DETAIL A SONY CODE EIAJ CODE JEDEC CODE 0.15 0.05 (0.2) (0.15) PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g DETAIL B LQFP-144P-L081 LQFP144-P-2020 - 126 - CXD2586R/-1 LQFP-144P-L141 144PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 108 109 73 72 1.7 MAX B A 144 1 0.5 0.1 0.05 0.22 0.05 36 0.1 M S S 0.1 S 37 (21.0) 0.22 0.05 0.5 } 0.2 0 to 10 DETAIL A DETAIL B 0.15 0.05 (0.2) (0.15) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L141 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 127 - |
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